Summary

As part of Cornell's FPGA & Hardware Accelerator Design course (ECE 5760), I designed and implemented a hardware drum synthesizer on an Intel Altera DE1-SoC FPGA. The core of the project is a real-time hardware solver for the 2D wave equation — the physical model governing how a drumhead vibrates when struck.

The 2D Wave Equation

A drumhead is modeled as a 2D elastic membrane with fixed boundary conditions. When struck, the membrane displacement u(x, y, t) evolves according to the wave PDE. The hardware solver discretizes this on a grid and iteratively updates each grid point using its neighbors — a computation that maps naturally to FPGA parallelism since adjacent points can be updated simultaneously.

Hardware Architecture

The design uses a pipelined grid update architecture in fixed-point arithmetic:

• The membrane grid is stored in on-chip M10K block RAM, with dual-port access for simultaneous read of neighbor points
• A pipelined arithmetic unit computes the wave equation update for each point per clock cycle
• The center-point displacement is sampled and sent to the I2S DAC for audio output
• Drum strikes are triggered via pushbuttons on the DE1-SoC, initiating an impulse at a configurable grid location

Leveraging FPGA parallelism allowed real-time audio synthesis — the grid update rate is high enough to produce audio-frequency output through the board's audio codec.