Summary

As part of Cornell's FPGA & Hardware Accelerator Design course (ECE 5760), I designed and implemented a parallelized Mandelbrot Set visualizer on an Intel Altera DE1-SoC FPGA. The project demonstrated hardware acceleration for a compute-intensive task: determining per-pixel escape iteration counts for a VGA-resolution rendering of the Mandelbrot set in real time.

How It Works

The Mandelbrot set is the set of complex numbers c for which the iteration z → z² + c remains bounded. For each pixel, the hardware computes this iteration in fixed-point complex arithmetic until it either escapes (magnitude > 2) or hits a maximum iteration count, then maps the result to a color. The key challenge is throughput: a 640×480 display requires 307,200 pixels per frame.

The FPGA solves this with a parallel array of compute units — each handling an independent pixel simultaneously. The number of parallel units is tuned to fit within the DE1-SoC's ALM budget while maximizing frames per second.

Results

The parallelized FPGA implementation achieved a significant speedup over a software reference on the HPS ARM core. Resource utilization and speedup plots are included in the image slider. The design also supported interactive zoom and pan via memory-mapped I/O from the HPS.