Cornell ECE 6745 · Project 2

DNA Alignment Chip

A custom chip that compares DNA.

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Meet the chip

A tiny chip built to read DNA.

The size

1 mm × 1 mm of custom silicon. 64 tiny calculators.

The speed

It compares DNA 66x faster, with 76x less energy.Simulated, versus the processor alone.

The team

The result

Back from the fab. Tested in the lab. Validation complete!

See through the chip

Does the plan match the silicon?

The real chip, under normal light.

Angle the light: the copper routing underneath shows.

Now lay our full design over it.

Strip it down to just the upper metal routing.

Melt it into the real chip…

Same routes. They match!

The fabricated DNA chip under the microscope

Validation day

Chip validation, in the lab.

Schmoo Plot

Validation complete! 163 MHz @ 1.8 V typical 200 MHz max tested 10 MHz passes at every voltage

Real test session · 25 min at 150x

VOLTAGE–V

CLOCK–MHz

RESULT–

0 / 162 tests

Clock (MHz)

columns = volts · rows = MHzpasssome failfail1.8 V

Tap a square.

Test board, supply swept 1.4 to 2.2 V, clock swept 1 to 200 MHz. Nominal supply is 1.8 V. Scroll to fill the plot one voltage at a time (order is illustrative).

The full flow

Every check, start to finish.

RTL simulation, two-state and four-state.

Synthesis, then gate-level simulation.

Place & route, timing and power.

DRC and LVS, then off to the foundry.

Full ASIC flow: RTL simulation, synthesis, gate-level simulation, place and route, static timing, power analysis, back-annotated simulation, DRC and LVS, then the semiconductor foundry

DNA Local Alignment Score Accelerator

Project 2 — ECE 6745 Complex Digital ASIC Design

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live simulation

DNA Local Alignment Accelerator

Two 16-base sequences stream into an 8×8 systolic array. Each anti-diagonal of the Smith-Waterman matrix is scored in one cycle.

Scoring is the real Smith-Waterman rule from the page (+1 match, −1 mismatch, −2 gap, floor 0). The animation shows the tiled anti-diagonal wavefront; the taped-out chip finishes in a fixed 77 cycles including overhead.

Project information

Course: ECE 6745 — Complex Digital ASIC Design
Date: March 2026 – April 2026
Team: Zarif Karim, Vaishnavi Vednere, Vinay Ivaturi
Technology: TSMC 180nm
Tapeout: 1mm × 1mm ASIC chip
Typical speed: 163 MHz at 1.8 V (nominal supply for class and testing)
Tools: PyMTL3, Synopsys VCS, Synopsys PT, Cadence Innovus (PnR), Mentor Calibre (DRC/LVS)
Presentation: Google Slides

66x Exec. time speedup

76x Energy reduction

77 Cycles to compute

10.3 mW Average power

163 MHz Typical speed @ 1.8 V

1.8 V Nominal supply (class & testing)

Smith-Waterman Systolic Array PyMTL3 TSMC 180nm Cadence Innovus DRC/LVS Clean Tapeout Bioinformatics

At a Glance

A tiny chip that compares DNA, fast.

16 → 1DNA letters in, one score out

66xfaster (simulated)

76xless energy (simulated)

163 MHztypical at 1.8 V

FPGA ✓proven before the fab

Validatedback from the fab, tested

Built by a team of three at Cornell (ECE 6745) in TSMC 180nm.

How Small?

1 mm × 1 mm. About 285 fit on a penny.

A US penny. About 285 chips fit on it.

Everyday things at the same scale. Sizes are approximate.

How It Matches DNA

Fill a grid. Every square scores the best of three. Biggest number wins.

+1letters matchA = A

−1letters differA ≠ G

−2skip a letterA – _

Never below 0. Each letter is 2 bits: A=00, C=01, G=10, T=11. Traceback (showing which letters matched) was left out to save space.

What We Tried

Four versions. One winner. Each bright square is a calculator.

V11 × 1

1 calculatorOne square at a time. Small, but slow.Fits, but slow

V28 × 1

8 calculatorsA row of eight at once. Couldn't hit the clock speed.Clock too slow

V316 × 16

256 calculatorsEvery square at once. Far too big.Too big

V48 × 8 tiled

64 calculators64 calculators sweep diagonal waves, tile by tile. Fits and hits the speed.The winner. This is what we built.

More calculators = fewer steps, but a bigger chip and a harder clock to hit. V4 hit the sweet spot.

The four design choices

Calculation Style

Row-chunk (baseline)
Anti-diagonal (final)

Pipelining

Combinational PE's
Sequential PE's

Data Streaming

Bulk load
Base forwarding

Dimensionality

16×16 array
8×8 tiled (final)

How It Works

64tiny calculators in an 8×8 grid

1 wavea whole diagonal is computed at once

4 tilesthe 16×16 problem, one tile at a time

Neighborspass results directly, no long wires

Performance

66xfaster than the processor alone (simulated)

76xless energy than the processor alone (simulated)

77 cyclesevery time, any DNA (770 ns)

10.3 mWaverage power

7.95 nJaverage energy per alignment

Why so efficient? A processor loops LOAD, ADD, BRANCH on every square. Our array just hands data to its neighbors. Designed for a 10 ns (100 MHz) clock. Averages are from 10 test cases.

FPGA First

We knew it worked before the chips came back.

Our designloaded onto an FPGA

DE0-SoCIntel Altera FPGA, driven over SPI

All correctevery function worked

An FPGA can be reprogrammed. A built chip can't be fixed. So we tested here first.

What We Learned

≈ 1 : 1controller grew as big as the 64 calculators

4xmore calculators for a full 16×16 array

No tripsto memory = way less energy

Next Up

66x faster. 76x less energy. Custom hardware wins, even in an older chip process.

Shrink the controller Longer DNA strands Show which letters matched Try a full 16×16 array Newer chip process