Project information
- Course: ECE 6745 — Complex Digital ASIC Design
- Date: February 1 – March 1, 2026
- Node: TSMC 180nm
- Tools: Icarus Verilog, Ngspice, Klayout (DRC/LVS/RCX), Verilator, Custom Synthesis & PnR
- Presentation: Google Slides
ASIC
Tapeout
TSMC 180nm
Popcount
Klayout
Custom PnR
Verilog
Summary
As part of Cornell's Digital ASIC Design course (ECE 6745), my group designed a 1µm × 1µm ASIC in the TSMC 180nm node targeting tapeout. The chip implements a popcount unit — a circuit that counts the number of 1s in an 8-bit input — a primitive common in machine learning, cryptography, and network processing workloads.
Design Flow
We built a fully custom RTL-to-GDSII flow from scratch rather than using a commercial EDA suite end-to-end. The major stages were:
- RTL Simulation: Icarus Verilog (4-state GL sim) and Verilator (2-state RTL sim) for functional correctness
- Schematic Simulation: Ngspice for analog-level cell verification
- Synthesis: Custom logic synthesis targeting the TSMC 180nm standard cell library
- Place & Route: Custom automated PnR with manual floorplanning
- Signoff: Klayout for DRC, LVS, and parasitic extraction (RCX)
Results
The chip passed DRC and LVS clean. Post-layout parasitic extraction and re-simulation confirmed functional correctness. The design is scheduled for physical tapeout through the Cornell TSMC 180nm shuttle run.