Project information
- Course: ECE 4740 — Intro to Digital VLSI
- Date: April 21 – May 17, 2025
- Tools: Cadence Virtuoso (Schematic & Layout), SPICE, DRC, LVS
- GitHub: zkarim28/alu
- Report: Final Report
- Poster: Final Poster
VLSI
Cadence Virtuoso
Dynamic Logic
ALU
SPICE
DRC/LVS
Layout
Summary
As part of Cornell's Digital VLSI course (ECE 4740), my team designed a high-speed 4-bit Arithmetic Logic Unit capable of performing 10 operations: ADD, SUB, MUL, AND, OR, XOR, SLL, SRL, and two comparison variants (G, GEQ). The focus was on optimizing performance using dynamic logic for speed while exploring static logic alternatives for power efficiency.
Design Process
The full design flow ran schematic-first through layout:
- Drew and verified each sub-cell (adder, shifter, logic gates) via SPICE simulation in Cadence Virtuoso
- Performed transistor-level layout for each cell, then verified via DRC and LVS
- Integrated sub-cells into the top-level ALU and re-ran SPICE post-extraction
Key Design Features
- Custom ripple-carry adder using mixed dynamic-static logic for minimum critical path delay
- Area-efficient barrel shifters for SLL and SRL operations
- Glitch mitigation techniques applied to the dynamic precharge network
- All cells layout-verified DRC/LVS clean before integration